`timescale 10ns/1ns
module TEST_Multicycle_Processor;
	reg iClk, iReset, Start;

	reg iMemInstructionWriteMode;
	reg [31:0] iMemAddress, iMemWriteData;

	wire [31:0] oInst0, oData1, oData2, oData5, oData16, oData17;

	Multicycle_Processor U0(.*);//positive edge triggered
	
	initial begin //clock generation, #1 = 10ns = 1clock
		#0 iClk <=1'b0;
		forever #0.5 iClk<=~iClk;
	end
	
	initial fork
		#0 {iMemInstructionWriteMode, iReset, Start}<=3'b100; //Write instructions to memory, while not starting.
		#0 iMemAddress<=32'd0; #0 iMemWriteData<=32'b00000000000000000001000000100000;
		#1 iMemAddress<=32'd1; #1 iMemWriteData<=32'b00111000000000010000000000000001;
		#2 iMemAddress<=32'd2; #2 iMemWriteData<=32'b00111000000001110000000000010000;
		#3 iMemAddress<=32'd3; #3 iMemWriteData<=32'b00000000010000010001000000100000;
		#4 iMemAddress<=32'd4; #4 iMemWriteData<=32'b10101100010000100000000010000000;
		#5 iMemAddress<=32'd5; #5 iMemWriteData<=32'b00000000010001110010000000101010;
		#6 iMemAddress<=32'd6; #6 iMemWriteData<=32'b00010000001001001111111111111100;
		#7 iMemAddress<=32'd7; #7 iMemWriteData<=32'b00000000000000000001000000100000;
		#8 iMemAddress<=32'd8; #8 iMemWriteData<=32'b00111000000001010000000000000000;
		#9 iMemAddress<=32'd9; #9 iMemWriteData<=32'b00000000010000010001000000100000;
		#10 iMemAddress<=32'd10; #10 iMemWriteData<=32'b00000000101000100010100000100000;
		#11 iMemAddress<=32'd11; #11 iMemWriteData<=32'b00000000010001110010000000101010;
		#12 iMemAddress<=32'd12; #12 iMemWriteData<=32'b00010000001001001111111111111100;
		#13 iMemAddress<=32'd13; #13 iMemWriteData<=32'b10101100000001010000000010010001;

		#14 {iReset, iMemInstructionWriteMode}<=2'b10; //Write ends and reset registers
		#15 iReset<=1'b0;

		#20 Start<=1'b1; //start computing at 205ns
		#21 Start<=1'b0;

	join

endmodule